Semiconductor Ecosystem

Arizona's Semiconductor Ecosystem

From sand to silicon — Arizona is home to the world's most advanced domestic chip manufacturing cluster, with $210B+ in investment and 65,000+ jobs across 95+ companies.

$210B+

Total Investment

95+

Companies

65,000+

Jobs

Active Fabs

Interactive Ecosystem Map

95 companies across 13 categories — hover or tap any pin to see company details, facility type, and investment data.

Fab / IDM Fabless / Design Packaging / OSAT Equipment OEM Materials / Chemicals Defense Services / Other

⛶ Open Full Ecosystem Map

Featured Companies

Five anchor companies anchoring Arizona's position at the frontier of domestic chip manufacturing and packaging.

TSMC Arizona

Phoenix

Wafer Fab — N4 / N3 / N2

$65B investment · 6,000+ jobs

TSMC's Fab 21 is America's most advanced semiconductor fab, producing Apple A16 and M4 chips at the 4nm node. Phase 2 (N3) is under construction, with N2 announced.

Intel Ocotillo Campus

Chandler

Wafer Fab — Intel 18A

$50B+ in AZ

Intel's Chandler campus has operated for 40+ years and remains one of the world's most advanced fabs. Fab 52 uses Intel 18A, the world's most advanced process node at 1.8nm class.

Amkor Technology

Peoria / Tempe

Advanced Packaging & Test

$2B facility

Amkor's new Peoria facility is America's most advanced chip packaging plant, performing OSAT services for Apple, NVIDIA, and other leading chip designers.

onsemi

Scottsdale

Power Semiconductors & SiC

HQ + R&D

onsemi's global headquarters in Scottsdale drives the design of silicon carbide (SiC) power chips critical for electric vehicles and renewable energy systems.

Microchip Technology

Chandler

MCU Design & IP

$9B revenue company

Founded and headquartered in Chandler, Microchip Technology is the world's leading maker of microcontrollers and mixed-signal semiconductors.

Full Supply Chain — 13 Categories

Every layer of the semiconductor value chain is represented in Arizona — from silicon fabs to chip design, advanced packaging, materials, equipment, and defense.

FAB / IDM

12 companies

TSMCIntelMicrochipNXPInfineononsemiEverspinADICompound Photonics

FABLESS / DESIGN

14 companies

ON Semi DesignMicrochip IPSemtechLatticeRambusRenesas

PACKAGING / OSAT

3 companies

Amkor HQAmkor OSATFlip Chip International

TEST / ASSEMBLY

3 companies

Amkor TestBenchmark ElectronicsIEC Electronics

SPECIALTY GASES

5 companies

Air ProductsLindeAir LiquideMesserMatheson

WET CHEMICALS

9 companies (Casa Grande cluster)

Merck KGaAFUJIFILMStella ChemifaTokuyamaKMG ChemicalsCMC Materials

MATERIALS / CMP

10 companies

EntegrisCabot MicroelectronicsSaint-GobainFerroVersum Materials

EQUIPMENT OEM

15 companies

ASMLApplied MaterialsLam ResearchKLAOnto InnovationAxcelis

FAB SERVICES

9 companies

BE SemiconductorCohuUltra Clean HoldingsPhoton DynamicsPrecision Castparts

DEFENSE

3 companies

HoneywellRaytheon RTXGeneral Dynamics

DISTRIBUTION

6 companies

Avnet HQArrow ElectronicsFuture ElectronicsTTI

IP / EDA

3 companies

SynopsysARMRambus

RESEARCH

3 institutions

Natcast/NSTC at ASUASU MacroTechnology WorksSEMI

The Casa Grande Chemical Cluster

Twenty-five miles south of Phoenix in Casa Grande and Pinal County, a deliberate supply chain strategy has taken shape: multiple international specialty chemical companies — including Merck KGaA, FUJIFILM Electronic Materials, Stella Chemifa, and Tokuyama — have co-located new manufacturing facilities specifically to supply TSMC's Fab 21 and Intel's Ocotillo Campus with ultra-pure wet chemicals. This kind of intentional supply chain co-location mirrors what has developed over decades in Taiwan, South Korea, and Japan — and it is now taking root in Arizona. The cluster reduces logistics costs and lead times for corrosive, temperature-sensitive chemicals that cannot easily be stored or transported over long distances.

An Educational Overview

Inside the World's Most Complex Machine

Semiconductors power every phone, car, and data center on Earth — yet almost no one knows how they're made. This is a high-level educational look at the remarkable, globe-spanning journey from desert sand to silicon chip. The real process involves thousands of substeps, specialized tools, and years of engineering — but this guide gives you the insight to understand why it matters.

Explore the Journey

Sibelco

Wacker Chemie

Photos: Wikimedia Commons (CC BY-SA)

Step 01

Sand & Silica Mining

It all begins with one of Earth's most abundant materials

Special quartz sand called silicon dioxide (SiO₂) is mined from deposits around the world. Not just any beach sand — this is ultra-pure quartz with over 99% silica content, found in places like North Carolina, Australia, and Norway. This sand is the raw material that eventually becomes the silicon inside every microchip on Earth.

Key Stakeholders

Sibelco (Belgium)The Quartz Corp (Norway/USA)Unimin (USA)

Feeds Into

Silicon metal producers→Chemical purification plants

REC Silicon

Wacker Chemie

OCI

Photos: Wikimedia Commons (CC BY-SA)

Step 02

Silicon Purification (Metallurgical Grade)

Sand is cooked into raw silicon at over 2,000°C

The quartz sand is smelted in massive electric arc furnaces at temperatures exceeding 2,000°C alongside carbon (like coal or wood chips). This chemical reaction strips away the oxygen, leaving behind metallurgical-grade silicon — about 98-99% pure. Think of it like refining crude oil, but for electronics.

Key Stakeholders

REC Silicon (Norway/USA)Wacker Chemie (Germany)Hemlock Semiconductor (USA)

Feeds Into

Polysilicon producers→Chemical plants

Hemlock Semiconductor

Wacker Chemie

OCI

Photos: Wikimedia Commons (CC BY-SA)

Step 03

Polysilicon Production (Electronic Grade)

Refined to 99.999999999% purity — cleaner than anything in nature

Metallurgical silicon isn't nearly pure enough for chips. It goes through a chemical process called the Siemens Process, where it's converted to trichlorosilane gas, purified, then redeposited as polysilicon rods — achieving 99.999999999% purity (that's eleven 9s!). For context, a single atom of contamination per billion could ruin a chip.

Key Stakeholders

Hemlock Semiconductor (USA)Wacker Chemie (Germany)OCI Company (South Korea)REC Silicon

Feeds Into

Crystal growers→Wafer manufacturers

Shin-Etsu

Siltronic

Sumco

Photos: Wikimedia Commons (CC BY-SA)

Step 04

Crystal Growth (Czochralski Process)

Molten silicon is pulled into a flawless cylindrical crystal

Polysilicon chunks are melted in a quartz crucible at 1,414°C. A tiny "seed crystal" of perfectly-aligned silicon is dipped into the melt and slowly pulled upward while rotating. As it rises, molten silicon clings to it and solidifies — growing a single, perfectly-ordered crystal cylinder called an ingot, up to 12 inches wide and 6 feet tall.

Key Stakeholders

Shin-Etsu Chemical (Japan)Sumco (Japan)Siltronic (Germany)GlobalWafers (Taiwan)

Feeds Into

Wafer slicing facilities→Polishing plants

Shin-Etsu

Siltronic

GlobalWafers

Photos: Wikimedia Commons (CC BY-SA)

Step 05

Ingot Slicing & Wafer Polishing

Diamond wire saws cut the ingot into mirror-smooth discs

The cylindrical silicon ingot is sliced into ultra-thin discs — called wafers — using diamond wire saws. Each wafer is about as thick as a credit card (725 micrometers). Then they're polished to an atomic-level mirror finish using chemical-mechanical planarization (CMP). A single scratch too small to see can destroy thousands of chips.

Key Stakeholders

Shin-Etsu ChemicalSumcoSiltronicSK Siltron (South Korea)

Feeds Into

Chip fabs (TSMC, Intel, Samsung)→Equipment makers (Disco Corp)

NVIDIA

Synopsys

Cadence

Photos: Wikimedia Commons (CC BY-SA)

Step 06

Chip Architecture & Design (EDA)

Engineers map billions of transistors before a single wafer is touched

Before a single chip is made, engineers design it entirely in software using Electronic Design Automation (EDA) tools. This can take 2-5 years and thousands of engineers. The design defines where billions of transistors will go — each one a tiny on/off switch smaller than a virus. The final "tape-out" design is sent to the fab like a massive digital blueprint.

Key Stakeholders

NVIDIAAppleQualcommAMDIntelSynopsysCadence Design SystemsSiemens EDA

Feeds Into

Photomask makers→Foundries

Toppan

Photronics

Hoya

Photos: Wikimedia Commons (CC BY-SA)

Step 07

Photomask Creation

Glass plates etched with circuit patterns — each one worth millions

The chip design is printed onto a photomask — a quartz plate with ultra-precise chrome patterns that act as a stencil for light. One advanced chip can require 80+ different photomasks, each made using electron-beam lithography at nanometer precision. A single mask can cost $100,000 or more.

Key Stakeholders

Photronics (USA)Toppan Photomasks (Japan)Hoya (Japan)Applied Materials (USA)

Feeds Into

Foundries (TSMC, Samsung, Intel)→Lithography equipment makers

TSMC

Samsung

Intel

Photos: Wikimedia Commons (CC BY-SA)

Step 08

Thermal Oxidation

The wafer is baked in oxygen to grow a nanometer-thin glass shield

The bare silicon wafer enters a furnace at 900–1,200°C in the presence of oxygen or steam. This grows a thin, perfectly uniform layer of silicon dioxide (glass) on the wafer's surface. This layer insulates different parts of the circuit from each other — like the insulation on electrical wires, but measured in nanometers.

Key Stakeholders

TSMCSamsung FoundryIntel FoundryGlobalFoundries

Feeds Into

Deposition equipment makers→Applied Materials→Lam Research

Applied Materials

Lam Research

Tokyo Electron

Photos: Wikimedia Commons (CC BY-SA)

Step 09

Thin Film Deposition (CVD / PVD / ALD)

Layers of material just atoms thick are deposited one by one

Incredibly thin layers of materials — metals, insulators, semiconductors — are deposited onto the wafer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). ALD can deposit a film literally one atom thick at a time. These layers build up the complex 3D structure of the chip, like printing a microscopic skyscraper.

Key Stakeholders

Applied MaterialsLam ResearchTokyo ElectronASM International

Feeds Into

Lithography step→Chemical suppliers (Air Products, Linde)

Shin-Etsu

JSR Corporation

DuPont

Photos: Wikimedia Commons (CC BY-SA)

Step 10

Photoresist Coating

A light-sensitive chemical is spun across the wafer surface

The wafer is coated with a light-sensitive chemical called photoresist — like covering it in photographic film. A spin coater applies a perfectly uniform layer just nanometers thick. This coating will react to light exposure, allowing the circuit pattern to be transferred from the photomask onto the wafer.

Key Stakeholders

JSR Corporation (Japan)Shin-Etsu ChemicalTokyo Ohka Kogyo (Japan)DuPont (USA)

Feeds Into

Lithography machines→Chemical suppliers

ASML

Canon

Nikon

Photos: Wikimedia Commons (CC BY-SA)

Step 11

Photolithography (EUV / DUV)

Extreme ultraviolet light prints circuit patterns smaller than a virus

This is the most critical — and most expensive — step in chip making. The wafer goes inside a lithography machine where light shines through the photomask, projecting the circuit pattern onto the photoresist. For cutting-edge chips, Extreme Ultraviolet (EUV) light at just 13.5 nanometers is used — shorter than an X-ray. ASML's EUV machines (costing $380 million each) are the only machines in the world that can do this.

Key Stakeholders

ASML (Netherlands — EUV monopoly)Canon (Japan)Nikon (Japan)TSMCSamsungIntel Foundry

Feeds Into

Etching step→Chemical suppliers→Zeiss (ASML lens supplier)

Lam Research

Tokyo Electron

Applied Materials

Photos: Wikimedia Commons (CC BY-SA)

Step 12

Etching

Chemicals or plasma carve the exposed pattern into the wafer surface

After the photoresist is exposed and developed, etching removes the unwanted material — either using corrosive chemicals (wet etching) or plasma gas (dry etching). This carves the actual circuit patterns into the wafer's layers with atomic precision. Modern chips require hundreds of etch steps, each removing material in patterns as small as 2 nanometers — 40,000 times thinner than a human hair.

Key Stakeholders

Lam Research (USA)Tokyo Electron (Japan)Applied MaterialsTSMCSamsungIntel

Feeds Into

Ion implantation step→Chemical waste treatment

Applied Materials

Axcelis

Photos: Wikimedia Commons (CC BY-SA)

Step 13

Ion Implantation & Doping

Atoms are fired at near-light speed into the silicon to alter its conductivity

Pure silicon doesn't conduct electricity well. To make transistors work, the silicon must be "doped" — bombarded with ions of elements like boron or phosphorus using an ion implanter. These foreign atoms are fired at the wafer at 1-5% the speed of light, embedding into the crystal lattice. This precisely controls where and how well electricity can flow.

Key Stakeholders

Applied MaterialsAxcelis Technologies (USA)Sumitomo Heavy Industries (Japan)

Feeds Into

Annealing step→Thermal processing

Applied Materials

Mattson Technology

Screen Holdings

Photos: Wikimedia Commons (CC BY-SA)

Step 14

Rapid Thermal Annealing

A millisecond flash of heat repairs crystal damage from ion implantation

After ion implantation, the silicon crystal is damaged — like a lawn after aerating. Rapid thermal annealing (RTA) heats the wafer to 1,000°C in milliseconds using high-powered lamps. This repairs the crystal damage and "activates" the dopant atoms, making them electrically effective. The heating must be fast to prevent dopants from spreading to the wrong places.

Key Stakeholders

Applied MaterialsMattson TechnologyScreen Holdings (Japan)

Feeds Into

Deposition→Subsequent lithography layers

Applied Materials

Entegris

Ebara

Photos: Wikimedia Commons (CC BY-SA)

Step 15

Chemical Mechanical Planarization (CMP)

The wafer surface is polished flat to within a single atom's height

After each major layer is built, the wafer surface becomes uneven. CMP polishes it back to perfect flatness using a combination of chemical slurries and mechanical abrasion — like sanding wood but at the nanometer scale. Without this step, subsequent layers would be printed on a crooked surface, causing defects. A chip may undergo CMP 20+ times during manufacturing.

Key Stakeholders

Applied MaterialsEbara (Japan)Entegris (USA)

Feeds Into

Next deposition/lithography cycle

Lam Research

Entegris

DuPont

Photos: Wikimedia Commons (CC BY-SA)

Step 16

Metallization & Interconnects

Copper wiring connects every transistor across dozens of stacked layers

Transistors alone don't do anything — they need to be connected. Metallization deposits ultra-thin copper or aluminum wires between transistors across dozens of layers. Modern chips have up to 15 layers of metal interconnects stacked on top of each other — like a city with 15 levels of roads. Copper is deposited using electroplating and precisely patterned.

Key Stakeholders

Lam ResearchEntegrisDuPontTSMCSamsungIntel

Feeds Into

Final wafer testing→Backend processing

Advantest

Teradyne

FormFactor

Photos: Wikimedia Commons (CC BY-SA)

Step 17

Wafer Testing (Wafer Sort)

Each die on the wafer is probed and graded before the wafer is cut

Before the wafer is cut apart, every single chip on it is tested using automated probe cards — tiny needles that touch each chip's contact pads and run thousands of electrical tests. Bad dies are marked with an ink dot. A wafer making 1,000 chips might have 80% yield (800 good chips) — the rest are scrapped.

Key Stakeholders

Advantest (Japan)Teradyne (USA)FormFactor (USA)TSMCSamsungIntel

Feeds Into

OSAT packaging companies→Wafer dicing

Applied Materials

Lam Research

Photos: Wikimedia Commons (CC BY-SA)

Step 18

Wafer Dicing & Die Separation

Diamond blades or lasers separate hundreds of chips from a single wafer

A diamond-tipped saw or high-powered laser cuts the wafer along the streets (channels between chips) into individual dies. Each die is a complete, functional chip. The wafer is mounted on sticky tape during dicing so chips don't fly everywhere. Dies are then sorted, inspected, and shipped to packaging facilities.

Key Stakeholders

Disco Corporation (Japan)Tokyo Seimitsu (Japan)Han's Laser (China)

Feeds Into

OSAT companies (Amkor, ASE Group)→Advanced packaging fabs

Amkor Technology

ASE Group

JCET

Photos: Wikimedia Commons (CC BY-SA)

Step 19

Advanced Packaging (OSAT)

The bare die is bonded, encased, and wired for the outside world

The bare chip die must be packaged to protect it and connect it to the outside world. OSAT companies attach the die to a substrate, connect it via wire bonding or flip-chip bumps, and encase it in epoxy. Advanced packaging (like TSMC's CoWoS used for NVIDIA's AI chips) stacks multiple dies together using through-silicon vias (TSVs) — creating 3D chip "towers." Companies like Amkor Technology and ASE Group operate massive OSAT facilities across Asia and North America.

Key Stakeholders

Amkor Technology (USA/Arizona)ASE Group (Taiwan)JCET (China)TSMC (advanced packaging)

Feeds Into

Final testing→OEM customers (Apple, NVIDIA, Qualcomm)

Amkor Technology

Advantest

Teradyne

TSMC

Photos: Wikimedia Commons (CC BY-SA)

Step 20

Final Testing, Burn-In & Global Shipment

Every chip runs at full stress for hours before it leaves the factory

Packaged chips undergo rigorous final testing — functional tests, burn-in (running at high temperature and voltage for hours to find early failures), and stress tests. Chips that pass are binned by performance and speed grade, then shipped worldwide. A chip designed in California, built in Taiwan, packaged in Malaysia, and tested in Arizona might end up in a phone assembled in China — then sold in Europe. This global supply chain is one of humanity's most complex engineering achievements.

Key Stakeholders

Amkor TechnologyASE GroupAdvantestTeradyneAppleNVIDIAQualcommAMD

Feeds Into

Smartphones→Data centers→Automobiles→Defense systems→Medical devices